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1. general description the pca9620 is a peripheral device which interf aces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to eight backplanes, 60 segments, and up to 480 elements. the pca9620 is compatible with most microproce ssors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized using a display ram with auto-incremented addressi ng and display memory switching. the pca9620 features an internal charge pump with internal capacitors for on-chip generation of the lcd driving voltages 2. features and benefits ? aec q100 grade 2 compliant for automotive applications ? low power consumption ? extended operating temperature range from ? 40 ? c to +105 ? c ? 60 segments and 8 backplanes allowing to drive: ? up to 60 7-segment alphanumeric characters ? up to 30 14-segment alphanumeric characters ? any graphics of up to 480 elements ? 480-bit ram for display data storage ? selectable backplane drive configuration: st atic, 2, 4, 6, or 8 backplane multiplexing ? programmable internal charge pump for on-chip lcd voltage generation up to 3 ? v dd2 ? 400 khz i 2 c-bus interface ? selectable linear temperature compensation of v lcd ? selectable display bias configuration ? wide range for digital and analog power supply: from 2.5 v to 5.5 v ? wide lcd supply range: from 2.5 v for lo w threshold lcds and up to 9.0 v for high threshold (automobile) twisted nematic lcds ? display memory bank switching in st atic, duplex, and quadruplex drive modes ? programmable frame frequency in steps of 10 hz in the range of 60 hz to 300 hz; factory calibrated with a tolerance of ? 15 % covering the whole temperature and voltage range ? selectable inversion scheme for lcd driving waveforms: frame or line inversion ? integrated temperature sensor with temperature readout ? on chip calibration of intern al oscillator frequency and v lcd pca9620 60 x 8 lcd high-drive segme nt driver for automotive and industrial rev. 2 ? 8 november 2011 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 19 on page 72 .
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 2 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 3. applications ? automotive ? instrument cluster ? car radio ? climate control units ? industrial ? machine control systems ? measuring equipment ? signage ? information boards ? panels 4. ordering information 5. marking table 1. ordering information type number package name description version PCA9620H/q900/1 lqfp80 plastic low pr ofile quad flat package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 pca9620u/5ga/q1 bare die 80 bonding pads pca9620u table 2. marking codes type number marking code PCA9620H PCA9620H/q900 pca9620u pc9620-1
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 3 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 6. block diagram (1) the charge pump can generate a maximum output voltage of 3 ? v dd2 . fig 1. block diagram of pca9620 013aaa246 lcd voltage selector clock select and timing oscillator power-on reset clk scl sda a0 backplane outputs display control bp0 to bp7 display segment outputs display register output bank select 60 s0 to s59 pca9620 lcd bias generator v ss v lcd command decoder write data control a1 v dd1 v dd2 charge pump (1) (voltage multiplier) t1 t2 temperature sensor t3 i 2 c-bus controller data pointer, auto increment display ram
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 4 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 7. pinning information 7.1 pinning top view. for mechanical details, see figure 58 on page 63 . fig 2. pin configuration for lqfp80 (PCA9620H) PCA9620H s20 sda s21 scl s22 a1 s23 a0 s24 clk s25 t3 s26 t2 s27 t1 s28 v ss s29 v dd1 s30 v dd2 s31 v lcd s32 bp7 s33 bp6 s34 bp5 s35 bp4 s36 bp3 s37 bp2 s38 bp1 s39 bp0 s40 s19 s41 s18 s42 s17 s43 s16 s44 s15 s45 s14 s46 s13 s47 s12 s48 s11 s49 s10 s50 s9 s51 s8 s52 s7 s53 s6 s54 s5 s55 s4 s56 s3 s57 s2 s58 s1 s59 s0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 013aaa244
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 5 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial viewed from active side. for mechanical details, see figure 59 on page 64 . fig 3. pin configuration for pca9620u (bare die) pca9620u s20 sda s21 scl s22 a1 s23 a0 s24 clk s25 t3 s26 t2 s27 t1 s28 v ss s29 v dd1 s30 v dd2 s31 v lcd s32 bp7 s33 bp6 s34 bp5 s35 bp4 s36 bp3 s37 bp2 s38 bp1 s39 bp0 s40 s19 s41 s18 s42 s17 s43 s16 s44 s15 s45 s14 s46 s13 s47 s12 s48 s11 s49 s10 s50 s9 s51 s8 s52 s7 s53 s6 s54 s5 s55 s4 s56 s3 s57 s2 s58 s1 s59 s0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 013aaa510
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 6 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 7.2 pin description [1] when the internal v lcd generation is used, this pin drives the v lcd voltage. in this case pin v lcd is an output. when the external supply is requested, then pin v lcd is an input and v lcd can be supplied to it. in this case, the internal charge pump must be disabled (see table 8 on page 9 ). table 3. pin description symbol pin type description s0 to s59 61 to 80 and 1 to 40 output lcd segment bp0 to bp7 41 to 48 output lcd backplane v lcd 49 supply/output [1] lcd supply voltage v dd2 50 supply supply voltage 2 (charge pump) v dd1 51 supply supply voltage 1 (analog and digital) v ss 52 supply ground supply voltage t1 to t3 53 to 55 input test pins; must be tied to v ss in applications clk 56 input/output internal oscillator output, external oscillator input a0, a1 57, 58 input i 2 c-bus slave address selection bit scl 59 input i 2 c-bus serial clock sda 60 input/output i 2 c-bus serial data
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 7 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8. functional description the pca9620 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to 480 elements. 8.1 commands of pca9620 the pca9620 is controlled by 22 commands, which are defined in table 4 . any other combinations of operation code bits that are not mentioned in this document may lead to undesired operation modes of pca9620. 8.1.1 command: initialize this command generates a chip-wide reset which resets all command values to their default values (see table 25 on page 17 ). it must be sent to the pca9620 after power-on. after this command is sent, it is possible to send additional commands without the need to re-initialize the interface. reset takes 100 ns to complete. for further information, see section 8.3 on page 16 . table 4. commands of pca9620 command name bits reference 7 6 5 4 3 2 1 0 initialize 00111010 section 8.1.1 otp-refresh 11010000 section 8.1.2 oscillator-ctrl 110011coeosc section 8.1.3 charge-pump-ctrl110000cpe cpc section 8.1.4 temp-msr-ctrl 110010tce tme section 8.1.5 temp-comp-sla00011sla[2:0] ta b l e 2 9 temp-comp-slb00100slb[2:0] temp-comp-slc00101slc[2:0] temp-comp-sld00110sld[2:0] set-vpr-msb 0 1 0 0 vpr[7:4] section 8.1.6 set-vpr-lsb 0 1 0 1 vpr[3:0] display-enable 0 0 1 1100e section 8.1.7 set-mux-mode00000m[2:0] section 8.1.8 set-bias-mode 110001b[1:0] section 8.1.9 load-data-pointer 1 0 p[5:0] section 8.1.10 frame-frequency 0 1 1 f[4:0] section 8.1.11 input-bank-select 0 0 0 0 1 ib[2:0] section 8.1.12.1 output-bank-select 0 0 0 1 0 ob[2:0] write-ram-data b[7:0] section 8.1.13 temp-read td[7:0] section 8.1.14 , section 8.4.7 invmode_cpf_ctrl110101lf cpf section 8.1.15 temp-filter 1101001tfe section 8.1.16
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 8 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.1.2 command: otp-refresh in order to achieve the specified accuracy of v lcd , the frame frequency, and the temperature measurement, each ic is calibrated during production and testing of the device. this calibration is performed on eprom cells called one time programmable (otp) cells. these cells are read by the device at power-on, after a reset, and every time when the initialize command or the otp-refresh command is sent. this command will take approximately 10 ms to finish. 8.1.3 command: oscillator-ctrl the oscillator-ctrl command swit ches between internal and ex ternal oscillator and enables or disables pin clk. [1] default value. table 5. initialize - initialize command bit description bit symbol value description 7 to 0 - 00111010 fixed value table 6. otp-refresh - otp-re fresh command bit description bit symbol value description 7 to 0 - 11010000 fixed value table 7. oscillator-ctrl - oscillat or control command bit description for further information, see section 8.5 on page 40 . bit symbol value description 7 to 2 - 110011 fixed value 1 coe control pin clk 0 [1] clock signal not available on pin clk; pin clk is in 3-state and may be left floating 1 clock signal available on pin clk 0 osc oscillator source 0 [1] internal oscillator running 1 external oscillator used; pin clk becomes an input
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 9 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.1.4 command: charge-pump-ctrl the charge-pump-ctrl command enables or disables the internal v lcd generation and controls the charge pump voltage multiplier setting. [1] default value. 8.1.5 command: temp-msr-ctrl the temp-msr-ctrl command enables or disables the temperature measurement block and the temperature compensation of v lcd . [1] default value. 8.1.6 command: set-vpr-msb and set-vpr-lsb with these two instructions, it is possible to set the target v lcd voltage for the internal charge pump, see section 8.4.3 on page 33 . [1] default value. table 8. charge-pump-ctrl - charge pump control command bit description bit symbol value description 7 to 2 - 110000 fixed value 1 cpe charge pump switch 0 [1] charge pump disabled; no internal v lcd generation; external supply of v lcd 1 charge pump enabled 0 cpc charge pump voltage multiplier setting 0 [1] v lcd = 2 ? v dd2 1v lcd = 3 ? v dd2 table 9. temp-msr-ctrl - temperature measurement control command bit description for further information, see section 8.4.8 on page 38 . bit symbol value description 7 to 2 - 110010 fixed value 1 tce temperature compensation switch 0 no temperature compensation of v lcd possible 1 [1] temperature compensation of v lcd possible 0 tme temperature measurement switch 0 temperature measurement disabled; no temperature readout possible 1 [1] temperature measurement enabled; temperature readout possible table 10. set-vpr-msb - set vpr msb command bit description bit symbol value description 7 to 4 - 0100 fixed value 3 to 0 vpr[7:4] 0000 [1] to 1111 the four most si gnificant bits of vpr[7:0]
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 10 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] default value. 8.1.7 command: display-enable [1] default value. 8.1.8 command: set-mux-mode [1] default value. 8.1.9 command: set-bias-mode [1] default value. 8.1.10 command: load-data-pointer the load-data-pointer command defines one of the 60 display ram addresses where the following display data will be sent to. for further in formation, see section 8.9.1 on page 43 . table 11. set-vpr-lsb - set vp r lsb command bit description bit symbol value description 7 to 4 - 0101 fixed value 3 to 0 vpr[3:0] 0000 [1] to 1111 the four least significant bits of vpr[7:0] table 12. display-enable - display enable command bit description bit symbol value description 7 to 1 - 0011100 fixed value 0e 0 [1] display disabled; backplane and segment outputs are internally connected to v ss 1 display enabled table 13. set-mux-mode - set multiplex drive mode comman d bit description bit symbol value description 7 to 3 - 00000 fixed value 2 to 0 m[2:0] 000 [1] , 011, 110, 111 1:8 multiplex drive mode: 8 backplanes 001 static drive mode: 1 backplane 010 1:2 multiplex drive mode: 2 backplanes 100 1:4 multiplex drive mode: 4 backplanes 101 1:6 multiplex drive mode: 6 backplanes table 14. set-bias-mode - set bias mode command bit description bit symbol value description 7 to 2 - 110001 fixed value 1 to 0 b[1:0] 00 [1] , 01 1 4 bias 11 1 3 bias 10 1 2 bias
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 11 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.1.11 command: frame-frequency with the frame-frequency command, the frame frequency and the out put clock frequency can be configured. [1] nominal frame frequency calculated for the default clock frequency of 9600 hz. [2] duty cycle definition: % high-level time : % low-level time. [3] default value. table 15. load-data-pointer - load data pointer command bit description bit symbol value description 7 to 6 - 10 fixed value 5 to 0 p[5:0] 000000 to 111111 6-bit binary value of 0 to 59 table 16. frame frequency - frame frequency and output clock frequency command bit description bit symbol value description 7 to 5 - 011 fixed value 4 to 0 f[4:0] see ta b l e 1 7 nominal frame frequency (hz) table 17. frame frequency values f[4:0] nominal frame frequency, f fr (hz) [1] resultant oscillator frequency, f osc (hz) duty cycle (%) [2] 00000 60 2880 20 : 80 00001 70 3360 7 : 93 00010 80 3840 47 : 53 00011 91 4368 40 : 60 00100 100 4800 33 : 67 00101 109 5232 27 : 73 00110 120 5760 20 : 80 00111 129.7 6226 13 : 87 01000 141.2 6778 5 : 95 01001 150 7200 50 : 50 01010 160 7680 47 : 53 01011 171.4 8227 43 : 57 01100 177.8 8534 41 : 59 01101 192 9216 36 : 64 01110 [3] 200 9600 33 : 67 01111 208.7 10018 30 : 70 10000 218.2 10474 27 : 73 10001 228.6 10973 23 : 77 10010 240 11520 20 : 80 10011 252.6 12125 16 : 84 10100, 10101 266.7 12802 10 : 90 10110, 10111 282.4 13555 5 : 95 11000 to 11111 300 14 400 50 : 50
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 12 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.1.12 bank select commands for multiplex drive modes 1:4, 1:2 and static driv e mode, it is possible to write data to one area of the ram while displaying from another. these areas are named as ram banks. input and output banks can be set independently from one another with the input-bank-select and the output-bank-select command. for further information, see section 8.9.2 on page 48 . 8.1.12.1 command: input-bank-select [1] not applicable for multiplex drive mode 1:6 and 1:8. [2] default value. 8.1.12.2 command: output-bank-select [1] not applicable for multiplex drive mode 1:6 and 1:8. [2] default value. table 18. input-bank-select - input ba nk select command bit description [1] bit symbol value description 7 to 3 - 00001 fixed value 2 to 0 ib[2:0] selects ram bank to write to static drive mode 1:2 drive mode 1:4 drive mode 000 [2] bank 0: ram-row 0 bank 0: ram-rows 0 and 1 bank 0: ram-rows 0, 1, 2, and 3 001 bank 1: ram-row 1 010 bank 2: ram-row 2 bank 2: ram-rows 2 and 3 011 bank 3: ram-row 3 100 bank 4: ram-row 4 bank 4: ram-rows 4 and 5 bank 4: ram-rows 4, 5, 6, and 7 101 bank 5: ram-row 5 110 bank 6: ram-row 6 bank 6: ram-rows 6 and 7 111 bank 7: ram-row 7 table 19. output-bank-select - output bank select command bit description [1] bit symbol value description 7 to 3 - 00010 fixed value 2 to 0 ob[2:0] selects ram bank to read from to the lcd static drive mode 1:2 drive mode 1:4 drive mode 000 [2] bank 0: ram-row 0 bank 0: ram-rows 0 and 1 bank 0: ram-rows 0, 1, 2, and 3 001 bank 1: ram-row 1 010 bank 2: ram-row 2 bank 2: ram-rows 2 and 3 011 bank 3: ram-row 3 100 bank 4: ram-row 4 bank 4: ram-rows 4 and 5 bank 4: ram-rows 4, 5, 6, and 7 101 bank 5: ram-row 5 110 bank 6: ram-row 6 bank 6: ram-rows 6 and 7 111 bank 7: ram-row 7
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 13 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.1.13 command: write-ram-data the write-ram-data command writes data byte-wise to the ram. after power-on reset (por) the ram content is random and should be brought to a defined status by clearing it (setting it logic 0). [1] for this command bit rs of the control byte has to be set logic 1 (see table 33 on page 54 ). more information about the display ram can be found in section 8.9 on page 42 . 8.1.14 command: temp-read the temp-read command allows reading out the temperature values measured by the internal temperature sensor. [1] for this command bit r/w of the i 2 c-bus slave address byte has to be set logic 1 (see table 32 on page 53 ). 8.1.15 command: invmode_cpf_ctrl the invmode_cpf_ctrl command allows changing the drive scheme inversion mode and the charge pump frequency. the waveforms used to drive lcd displays inherently produce a dc voltage across the display cell. the pca9620 compensates for the dc voltage by inverting the waveforms on alternate frames or alternate lines. the choice of compensation method is determined with the lf bit. [1] default value. table 20. write-ram-data - write ram data command bit description [1] bit symbol value description 7 to 0 b[7:0] 00000000 to 11111111 writing data byte-wise to ram table 21. temp-read - temperature readout command bit description [1] for further information, see table 9 on page 9 and section 8.4.7 on page 37 . bit symbol value description 7 to 0 td[7:0] 00000000 to 11111111 readout representing the digital temperature table 22. invmode_cpf_ctrl - inversion mode and charge pump frequency prescaler command bit description bit symbol value description 7 to 2 - 110101 fixed value 1 lf set inversion mode 0 [1] line inversion mode 1 frame inversion mode 0 cpf set charge pump oscillator frequency 0 [1] f osc(cp) ~1mhz 1f osc(cp) ~ 500 khz
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 14 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial in frame inversion mode, the dc value is compensated across two frames and not within one frame. changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. frame inversion may not be suitable for all applications. the rms voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. the waveforms of figure 16 on page 25 to figure 22 on page 31 are showing line inversion mode. figure 23 on page 32 shows one example of frame inversion. 8.1.16 command: temp-filter [1] default value. 8.2 possible display configurations the pca9620 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of lcd segment or dot matrix displays (see figure 4 ). it can directly drive any static or multiplexed lcd containing up to eight backplanes and up to 60 segments. the display configurations possible with t he pca9620 depend on the number of active backplane outputs required. a selection of po ssible display configurations is given in ta b l e 2 4 . table 23. temp-filter - digital temper ature filter command bit description bit symbol value description 7 to 1 - 1101001 fixed value 0 tfe digital temperature filter switch 0 [1] digital temperature filter disabled; the unfiltered digital value of td[7:0] is immediately available for the readout and v lcd compensation, see section 8.4.7 on page 37 1 digital temperature filter enabled
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 15 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial all of the display configurations in ta b l e 2 4 can be implemented in the typical systems shown in figure 5 (internal v lcd ) and in figure 6 (external v lcd ). fig 4. example of displa ys suitable for pca9620 table 24. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment 14-segment 8 480 60 30 480 dots (8 ? 60) 6 320 45 22 360 dots (6 ? 60) 4 240 30 15 240 dots (4 ? 60) 2 120 15 7 120 dots (2 ? 60) 1607360dots (1 ? 60) v dd1 from 2.5 v to 5.5 v and v dd2 from 2.5 v to 5.5 v. fig 5. typical system configuration when using the internal v lcd generation 7-segment with dot 14-segment with dot and accent 013aaa312 dot matrix host processor/ micro- controller r t r 2c b sda scl 60 segment drives 8 backplanes lcd panel (up to 480 elements) pca9620 a0 a1 v dd1 v ss v ss 013aaa247 v dd2 v lcd v dd2 v dd1 clk n.c.
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 16 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the host microcontroller maintains the two line i 2 c-bus communication channel with the pca9620. the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connection s required to complete the system are the power supplies (v dd1 , v dd2, v ss , v lcd ), the external capacitors, and the lcd panel selected for the application. the minimum recommended values for external capacitors on v dd1 , v dd2 , and v lcd are nominal 100 nf. when using bigger capacitors, especially on the v lcd , the generated ripple will be consequently smaller. however it will take longer for the internal charge pump to reach the target v lcd voltage first. if v dd1 and v dd2 are connected externally, the capacitors on v dd1 and v dd2 can be replaced by a single capacitor with a minimum value of 200 nf. remark: in the case of insufficient decoupling, ripple of v dd1 and v dd2 will create additional v lcd ripple. the ripple on v lcd can be reduced by making the v ss connection as low-ohmic as possible. excessive ripple on v lcd may cause flicker on the display. 8.3 start-up and shut-down 8.3.1 power-on reset (por) at power-on, the pca9620 resets to starting conditions as follows: 1. all backplane outputs are set to v ss . 2. all segment outputs are set to v ss . 3. selected drive mode is: 1:8 with 1 4 bias. 4. input and output bank selectors are reset. 5. the i 2 c-bus interface is initialized. 6. the data pointer is cleared (set logic 0). 7. the internal oscillator is runn ing; no clock signal is available on pin clk; pin clk is in 3-state. 8. temperature measurement is enabled. v dd1 from 2.5 v to 5.5 v, v dd2 from 2.5 v to 5.5 v and v lcd from 2.5 v to 9.0 v. fig 6. typical system configurati on when using an external v lcd host processor/ micro- controller r t r 2c b sda scl 60 segment drives 8 backplanes lcd panel (up to 480 elements) pca9620 a0 a1 v dd1 v ss v ss 013aaa248 v lcd v lcd v dd2 v dd1 clk n.c.
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 17 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 9. temperature filter is disabled. 10. the internal v lcd voltage generation is disabled. the charge pump is switched off. 11. the v lcd temperature compensation is enabled. 12. the display is disabled. remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. the first command sent to the device after the power-on event must be the initialize command (see section 8.1.1 on page 7 ). after power-on reset (por) and before enabling the display, the ram content should be brought to a defined status ? by clearing it (setting it all logic 0) or ? by writing meaningful content (for example, a graphic) otherwise unwanted display artifacts may appear on the display. table 25. reset states bits labeled - are undefined at power-on. command name bits 7 6 5 4 3 2 1 0 initialize 0 0 1 1 1 0 1 0 otp-refresh 11010000 oscillator-ctrl 11001100 charge-pump-ctrl 1 1 0 0 0 0 0 0 temp-msr-ctrl 1 1 0 0 1 0 1 1 temp-comp-sla 00011000 temp-comp-slb 00100000 temp-comp-slc 00101000 temp-comp-sld 00110000 set-vpr-msb 01000000 set-vpr-lsb 01010000 display-enable 0 0 1 1 1 0 0 0 set-mux-mode 00000000 set-bias-mode 11000100 load-data-pointer 1 0 0 0 0 0 0 0 frame-frequency 0 1 1 0 1 1 1 0 input-bank-select 00001000 output-bank-select 0 0 0 1 0 0 0 0 write-ram-data - - - - - - - - temp-read 01000000 invmode_cpf_ctrl11010100 temp-filter 11010010
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 18 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.3.2 recommended start-up sequences this chapter describes how to proceed with the initialization of the chip in different application modes. (1) this time depends on the external capacitor on pin v lcd . for a capacitor of 100 nf a delay of 5 ms to 15 ms is expected. when using the internal v lcd generation, the display must not be enabled before the generation of v lcd with the internal charge pump is completed. otherwise unwanted display artifacts may appear on the display. (2) ram data may be written before or during the ramp-up of v lcd . fig 7. recommended start-up sequence when using the internal charge pump and the internal clock signal wait 1 ms start power-on v dd1 and v dd2 at the same time 013aaa249 set vpr register to desired v lcd value set multiplication factor for charge pump and enable it wait till v lcd reaches programmed value (1) write ram content to be displayed and enable the display (2) stop initiate an otp-refresh initialize command
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 19 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial fig 8. recommended start-up sequence when using an external supplied v lcd and the internal clock signal (1) the external clock signal can be a pplied after the generation of the v lcd voltage as well. (2) this time depends on the external capacitor on pin v lcd . for a capacitor of 100 nf a delay of 5 ms to 15 ms is expected. (3) ram data may be written before or during the ramp-up of v lcd . fig 9. recommended start-up sequence when using the internal charge pump and an external clock signal wait 1 ms start power-on v dd1 , v dd2 , and v lcd at the same time initialize command 013aaa250 write ram content to be displayed and enable the display stop initiate an otp-refresh wait 1 ms start power-on v dd1 and v dd2 at the same time initialize command 013aaa251 set vpr register to desired v lcd value wait till v lcd reaches programmed value (2) write ram content to be displayed and enable the display (3) stop apply external clock signal to pin clk; set osc bit logic 1 (1) (1) initiate an otp-refresh set multiplication factor for charge pump and enable it
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 20 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.3.3 recommended power-down sequences with the following sequences, the pca9620 can be set to a state of minimum power consumption, called power-down mode. fig 10. recommended start-up sequence when using an external supplied v lcd and an external clock signal wait 1 ms start initialize command 013aaa252 write ram content to be displayed and enable the display stop apply external clock signal to pin clk; set osc bit logic 1 power-on v dd1 , v dd2 , and v lcd at the same time initiate an otp-refresh fig 11. recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal stop genera- tion of v lcd by setting bit cpe logic 0 start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa253 stop
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 21 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial fig 12. recommended power-down sequence when using an external supplied v lcd and the internal clock signal fig 13. recommended power-down sequence when using the internal charge pump and an external clock signal start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa254 stop stop genera- tion of v lcd by setting bit cpe logic 0 start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa255 stop external clock may be switched off bring pin clk to 3-state by setting bit osc and bit coe logic 0
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 22 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial remark: it is necessary to run the power-down sequence before removing the supplies. depending on the application, care must be ta ken that no other signals are present at the chip input or output pins when removing the supplies (refer to section 10 on page 55 ). otherwise it may cause unwanted display ar tifacts. the pca9620 will not be damaged by uncontrolled removal of supply voltages remark: static voltages across the liquid crystal display can build up when the external lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd1 or v dd2 ) is off, or vice versa. it may cause unwanted display artifacts. to avoid such artifacts, external v lcd , v dd1 , and v dd2 must be applied or removed together. remark: a clock signal must always be supplied to the device when the device is active; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. it is recommended to first disable the display and afterwards to remove the clock signal. 8.4 lcd voltage 8.4.1 lcd voltage selector the lcd voltage selector co-ordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the set-bias-mode command (see table 14 on page 10 ) and the set-mux-mode command (see table 13 on page 10 ). intermediate lcd biasing voltages are obtained from an internal voltage divider. the biasing configurations that app ly to the preferred modes of operation, together with the biasing characteristics as functions of v lcd and the resulting discrimination ratios (d), are given in table 26 . discrimination is a term which is defined as the ratio of the v on(rms) and v off(rms) across a segment. it can be thought of as a measurement of contrast. fig 14. recommended power-down sequence when using an external supplied v lcd and an external clock signal start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa256 stop bring pin clk to 3-state by setting bit osc and bit coe logic 0 external clock may be switched off
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 23 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] determined from equation 3 . [2] determined from equation 2 . [3] in these examples the discrimination fa ctor and hence the contrast ratios are smal ler. the advantage of these lcd drive mode s is a power saving from a reduction of the lcd voltage v lcd . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th(off) ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th(off) . bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias a = 3 for 1 4 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where v lcd is the resultant voltage at the lcd segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : table 26. lcd drive modes: summary of characteristics lcd drive mode number of: lcd bias configuration [1] v lcd [2] backplanes levels static 1 2 static 0 1 ? v on(rms) 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 2.828 ? v off(rms) 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 3.0 ? v off(rms) 1:2 multiplex [3] 25 1 4 0.395 0.729 1.845 2.529 ? v off(rms) 1:4 multiplex [3] 43 1 2 0.433 0.661 1.527 2.309 ? v off(rms) 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 3.0 ? v off(rms) 1:4 multiplex [3] 45 1 4 0.331 0.545 1.646 3.024 ? v off(rms) 1:6 multiplex [3] 63 1 2 0.456 0.612 1.341 2.191 ? v off(rms) 1:6 multiplex 6 4 1 3 0.333 0.509 1.527 3.0 ? v off(rms) 1:6 multiplex 6 5 1 4 0.306 0.467 1.527 3.266 ? v off(rms) 1:8 multiplex [3] 83 1 2 0.467 0.586 1.254 2.138 ? v off(rms) 1:8 multiplex [3] 84 1 3 0.333 0.471 1.414 3.0 ? v off(rms) 1:8 multiplex 8 5 1 4 0.293 0.424 1.447 3.411 ? v off(rms) v off rms ?? v lcd ---------------------- - v on rms ?? v lcd ---------------------- d v on rms ?? v off rms ?? ---------------------- - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd =
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 24 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) it should be noted that v lcd is sometimes referred as the lcd operating voltage. 8.4.1.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 15 . for a good contrast performance, the following rules should be followed: (4) (5) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 1 to equation 3 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. it is important to match the module properties to those of the driver in order to achieve optimum performance. v off rms ?? a 2 2a ? n + n 1a + ?? 2 ? ----------------------------- - v lcd = v on rms ?? v off rms ?? ---------------------- a1 + ?? 2 n 1 ? ?? + a1 ? ?? 2 n 1 ? ?? + ------------------------------------------- - = fig 15. electro-optical characteristic: relative transmission curve of the liquid v on rms ?? v th on ?? ? v off rms ?? v th off ?? ? v rms [v] 100 % 90 % 10 % off segment grey segment on segment v th(off) v th(on) relative transmission 013aaa494
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 25 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.2 lcd drive mode waveforms 8.4.2.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v on(rms) (t) = v lcd . v off(rms) (t) = 0 v. fig 16. static drive mode wave forms (line inversion mode) 013aaa207 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 26 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.2.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pca9620 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 17 and figure 18 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.791v lcd . v off(rms) (t) = 0.354v lcd . fig 17. waveforms for the 1:2 multiplex drive mode with 1 2 bias (line inversion mode) 013aaa208 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 ? v lcd ? v lcd ? v lcd /2 ? v lcd /2 sn sn+1 t fr
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 27 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.745v lcd . v off(rms) (t) = 0.333v lcd . fig 18. waveforms for the 1:2 multiplex drive mode with 1 3 bias (line inversion mode) 013aaa209 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 s n s n+1 t fr v ss v lcd 2v lcd /3 v lcd /3
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 28 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.2.3 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 19 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.577v lcd . v off(rms) (t) = 0.333v lcd . fig 19. waveforms for the 1:4 multiplex drive mode with 1 3 bias (line inversion mode) 013aaa211 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 -2v lcd /3 v lcd /3 -v lcd /3 -v lcd 0 v v lcd 2v lcd /3 -2v lcd /3 v lcd /3 -v lcd /3 -v lcd v ss v lcd 2v lcd /3 v lcd /3
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 29 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.2.4 1:6 multiplex drive mode when six backplanes are provided in the lcd, the 1:6 multiplex driv e mode applies. the pca9620 allows the use of 1 3 bias or 1 4 bias in this mode as shown in figure 20 and figure 21 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.509v lcd . v off(rms) (t) = 0.333v lcd . fig 20. waveforms for 1:6 multiplex drive mode with 1 3 bias (line inversion mode) 001aal399 state 1 state 2 lcd segments t fr v lcd bp0 2v lcd / 3 v lcd / 3 v ss v lcd bp1 2v lcd / 3 v lcd / 3 v ss v lcd bp2 2v lcd / 3 v lcd / 3 v ss v lcd bp3 2v lcd / 3 v lcd / 3 v ss v lcd bp4 2v lcd / 3 v lcd / 3 v ss v lcd bp5 2v lcd / 3 v lcd / 3 v ss v lcd sn (a) waveforms at driver (b) resultant waveforms at lcd segment 2v lcd / 3 v lcd / 3 v ss v lcd sn + 1 2v lcd / 3 v lcd / 3 v ss v lcd state 1 2v lcd / 3 v lcd / 3 v ss v lcd state 2 -v lcd 2v lcd / 3 -2v lcd / 3 v lcd / 3 -v lcd / 3 -v lcd -2v lcd / 3 -v lcd / 3 v ss
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 30 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.467v lcd . v off(rms) (t) = 0.306v lcd . fig 21. waveforms for 1:6 multiplex drive mode with 1 4 bias (line inversion mode) 001aal400 state 1 state 2 lcd segments v lcd 3v lcd / 4 v lcd / 4 v ss bp0 v lcd 3v lcd / 4 v lcd / 4 v ss bp1 v lcd 3v lcd / 4 v lcd / 4 v ss bp2 v lcd 3v lcd / 4 v lcd / 4 v ss bp3 v lcd 3v lcd / 4 v lcd / 4 v ss bp4 v lcd 3v lcd / 4 v lcd / 4 v ss bp5 v lcd -v lcd 3v lcd / 4 -3v lcd / 4 v lcd / 4 -v lcd / 4 v lcd / 2 -v lcd / 2 v ss v lcd v lcd / 2 v ss v lcd v lcd / 2 v ss state 2 v lcd -v lcd 3v lcd / 4 -3v lcd / 4 v lcd / 4 -v lcd / 4 v ss state 1 sn + 1 sn t fr (a) waveforms at driver (b) resultant waveforms at lcd segment
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 31 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.2.5 1:8 multiplex drive mode v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.424v lcd . v off(rms) (t) = 0.293v lcd . fig 22. waveforms for 1:8 multiplex drive mode with 1 4 bias (line inversion mode) 001aal398 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 sn sn + 1 state 1 state 2 v lcd 3v lcd / 4 state 1 state 2 lcd segments -v lcd v lcd / 2 v lcd / 4 v ss -v lcd / 4 -v lcd / 2 -3v lcd / 4 -v lcd -3v lcd / 4 -v lcd / 4 v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 2 v lcd v ss v lcd / 2 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss 3 lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd t fr (a) waveforms at driver (b) resultant waveforms at lcd segment
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 32 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn + 1 (t) ? v bp0 (t). v on(rms) (t) = 0.424v lcd . v off(rms) (t) = 0.293v lcd . fig 23. waveforms for 1:8 multiplex drive mode with 1 4 bias (frame inversion mode) 001aam359 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 sn sn + 1 state 1 state 2 state 1 t fr t fr frame n frame n+1 state 2 lcd segments v lcd 3/4 v lcd 1/4 v lcd v ss 1/4 v lcd 3/4 v lcd 1/2 v lcd 1/2 v lcd v lcd v lcd 3/4 v lcd 1/4 v lcd v ss 1/4 v lcd 3/4 v lcd 1/2 v lcd 1/2 v lcd v lcd v ss 1/2 v lcd v lcd v ss 1/2 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd (a) waveforms at driver (b) resultant waveforms at lcd segment
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 33 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial when eight backplanes are provided in the lcd, the 1:8 multiplex drive mode applies, as shown in figure 22 and figure 23 . 8.4.3 v lcd generation v lcd can be generated and controlled on the chip by using software commands. when the internal charge pump is used, the programmed v lcd is available on pin v lcd . the charge pump generates a v lcd of up to 3 ? v dd2 . the charge pump can be enabled or disabled with the cpe bit (see table 8 on page 9 ). with bit cpc, the charge pump mu ltiplier setting can be configured. the final value of v lcd is a combination of the programmed vpr[7:0] value and the output of the temperature compensation block, vt[7:0]. the system is shown in figure 24 . in equation 6 the main parameters are the programmed digital value term and the compensated temperature term. (6) 1. vpr[7:0] is the binary value of the programmed voltage. 2. vt[7:0] is the binary value of the temper ature compensated voltage. its value comes from the temperature compensation block and is a two?s complement which has the value 0h at 20 ? c. 3. m and n are fixed values (see ta b l e 2 7 ). figure 25 shows how v lcd changes with the programmed value of vpr[7:0]. fig 24. v lcd generation including temperature compensation 013aaa257 temperature readout ? 40 0 +80 +20 +50 temperature 0 offset sla slb slc sld 8 td 8 vpr[7:0] 8 v lcd n m table 27. parameters of v lcd generation symbol value unit m3 v n0.03v v lcd vpr 7 :0 ?? vt 7 :0 ?? + ?? n ? m + =
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 34 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial it has to be taken into account that the charge pump has to be configured (via bit cpc) properly to obtain the desired voltage range. for example, if v dd2 = 3.0 v and cpc is set to 2 ? v dd2 (logic 0) then the maximum theoretical value that the charge pump can reach is v lcd = 6.0 v. but in reality, lowe r values will be reached due to internal resistances, see section 8.4.5 . so, if the requested value for v lcd = 7.0 v then the charge pump has to be configured with cpc set to 3 ? v dd2 (logic 1). programmable range of vpr[7:0] is from 0h to ffh. this would allow achieving v lcd > 9.0 v, but the pca9620 has a built-in automatic limitation of v lcd at 9.0 v. if v dd2 is higher than 3.0 v, then it is important that vpr[7:0] is set to a value such that the resultant v lcd (including the temperature correction of vt[7:0]) is higher than v dd2 . 8.4.4 external v lcd supply v lcd can be directly supplied to the v lcd pin. in this case, the internal charge pump must not be enabled otherwise a high current may occur on pin v dd2 and pin v lcd . when v lcd is supplied externally, no internal temperature compensation occurs on this voltage even if bit tce is set logic 1 (see section 8.4.8 on page 38 ). the v lcd voltage which is supplied externally will be available at the segments and backplanes of the device through the chosen bias system. also programming the vpr[7:0] bit field has no effect on the v lcd which is externally supplied. (1) if v dd2 > 3.0 v then vpr[7:0] must be set so that v lcd > v dd2 . (2) automatic limitation for v lcd > 9.0 v. fig 25. v lcd programming of pca9620 (assuming vt[7:0] = 0h) 013aaa258 00 01 02 m v lcd vpr[7:0] 03 04 05 06 . . . . . . . . . . . . . . . . . . . . . . . . . . . fd fe ff n fc 9 v c8 c9 ca c7 (1) (2) v dd2
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 35 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.4.5 charge pump driving capability figure 26 illustrates the main factor determining how much curr ent the charge pump can deliver. the output resistance of the charge pump is specified in table 35 on page 57 . with these values, it can be calculated how much current the charge pump can drive under certain conditions. example: assuming that the no rmal operation point is at 25 ? c with v lcd = 7.0 v and v dd2 = 5.0 v and the charge pump is set to 2 ? v dd2 . then the theoretical value of v lcd is 10.0 v and the desired one is 7.0 v. the difference between the theoretical maximum value and desired one is 3.0 v. the char ge pump resistance is nominally 0.85 k ? . equation 7 shows the possible current that the charge pump could deliver: (7) the result of this example is: in cases where no extreme driving capabilit y is needed, a command is available for decreasing the charge pump frequency (see table 22 on page 13 ) and thus reducing the total current consumption. if the charge pump frequency is halved, then the driving capability is halved as well, wher eas the output re sistance doubles. 8.4.6 charge pump frequency settings and power efficiency the pca9620 offers th e possibility to use different fr equency settings for the charge pump. bit cpf controls the frequency at which the charge pump is running (see table 22 on page 13 ). this frequency has a direct influenc e on the current consumption of the ic but also on the charge pump driving capab ility. using a lower ch arge pump frequency decreases the current consumpt ion and the driving capability. the power efficiency of the charge pump determines in certain applications which frequency settings to choose for the cp f bit. concerning the example shown in figure 27 : the current consumption was measured with ? charge pump set to 2 ? v dd2 ? v dd2 =3.0v ? vpr[7:0] set to maximum to obtain the highest possible v lcd with this setup, which is close to 6.0 v the current load on pin v lcd determines the output power delivered by the ic: fig 26. charge pump model (used to characterize the driving strength) theoretical v lcd value v lcd = 2 v dd2 or v lcd = 3 v dd2 output resistance r o(cp) regulated desired v lcd this supplies the segments and backplanes 013aaa259 i load ? v lcd r ocp ?? ? = i load 3.0 v 0.85 k ?? 3.5 ma ==
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 36 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial (8) the current consumption on pin v dd2 determines the input power taken by the ic: (9) the ratio between these two numbers determ ines the charge pump power efficiency: (10) loading the charge pump with higher currents decreases the output voltage. this decrease is determined by the charge pump driving capability, respectively by the output resistance of the charge pump (see table 35 on page 57 ). the power efficiency calculation is only valid when the charge pump is running at its maximum peak frequency and regulates the generated v lcd voltage with full speed. in this case, the ripple on the v lcd voltage equals the internal charge pump frequency. approximately, this could also be calculated wit h the parameter of the output resistance of the charge pump (see table 35 on page 57 ), the load current, and the voltage needed to be provided by using equation 7 on page 35 . this value of i load is close to the value of the load current needed for the application. if the application runs with v dd2 = 3.0 v, the load currents are up to 400 ? a (dc measured), and the v lcd generated voltages are up to 5.0 v, then - concerning power efficiency - it would be the best to have a charge pump frequency set to half frequency. charge pump set to 2 ? v dd2 ; v dd2 =3v. (1) ? p , full charge pump frequency. (2) ? p , half charge pump frequency. (3) v lcd , full frequency. (4) v lcd , half frequency. fig 27. power efficiency of the charge pump p o i load v lcd ? = p i i dd2 v dd2 ? = ? p p o p i ? = i load (a) 0 1000 800 400 600 200 001aan027 50 70 90 p (%) 30 3 5 7 v lcd (v) 1 (3) (4) (1) (2)
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 37 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial if it is desired to change the charge pump frequency, it is recommended to make a graph like figure 27 and understand what the application requirements are. this would basically imply to find out what would be the maximum v lcd requirements and what would be the maximum load currents required. then it can be decided which is the best setting of bit cpf. tuning the charge pump frequency might be a difficult task to do. it requires good knowledge of the application in which t he ic is being used; therefore, nxp is recommending to keep the cpf bit set logic 0 to have the maximum charge pump frequency, thus having the maximum driving strength. 8.4.7 temperature readout the pca9620 has a built-in temperature sensor which provides an 8 bit digital value, td[7:0], of the ambient temperature. this value can be read through the i 2 c interface (see figure 50 on page 54 ). the actual temperature is determined from td[7:0] using equation 11 : (11) the measurement needs about 5 ms to complete. it is repeated periodically as soon as bit tme is set logic 1 (see table 9 on page 9 ). the time between measurements is linked to the system clock and hence varies with changes in the chosen frame frequency, see ta b l e 2 8 . due to the nature of a temperat ure sensor, oscillations on the v lcd may occur. to avoid it, a filter has been implemented in pca9620. the system is shown in figure 28 . like any other filtering, the digital temperature filter (see figure 28 ) introduces a certain delay in the measurement of temperature. this be havior is illustrated in figure 29 . table 28. temperature measurement update rate selected frame frequency temperature measurement update rate 60 hz 3.3 s 200 hz 1 s 300 hz 0.67 s fig 28. temperature measurement block with digital temperature filter t (c) 0.9375 td 7:0 ?? 40 ? ? = temperature measurement block digital temperature filter td[7:0] unfiltered td[7:0] filtered enabled or disabled by bit tfe to the readout register via i 2 c-bus and to the v lcd compensation block 013aaa260
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 38 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial this delay may cause undesired effects at start-up when the environment temperature may be different than the reset value of the pca9620 which is 20 c. in this case, it takes up to 30 s until the correct measured temperature value will be available. a control bit, tfe, is implemented to enable or disable th e digital temperature filter. this bit is set logic 0 by default which means that the filter is disabled and the unfiltered environment temperature value is available to calculate the desired v lcd . 8.4.8 temperature compensation of v lcd due to the temperature depen dency of the liquid crystal viscosity, the lcd controlling voltage v lcd might have to be adjusted at different temperatures to maintain optimal contrast. the temperature behavior of the liquid comes from the lcd manufacturer. the slope has to be set to compensate for the liquid behavior. internal temperature compensation may be enabled via bit tce. the ambient temperature range is split up into four equally sized regions and a different temperature coefficient can be applied to each (see figure 30 ). each coefficient can be selected from a choice of eight different slopes. each one of these coefficients (see ta b l e 2 9 ) may be independently selected via the temp-comp-sla to temp-comp-sld commands (see table 4 on page 7 ). (1) environment temperature, t1 ( ? c). (2) measured temperature, t2 ( ? c). (3) temperature deviation, ? t=t2 ? t1. fig 29. temperature measurement delay t (s) 0 160 120 80 40 001aal393 20 30 10 40 50 t (c) 0 (3) (1) (2) 4 8 0 12 16 t (c) (3) ?4
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 39 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] the relationship between the temperature coefficients ma to md and the slope factor is derived from the following equation: . [2] default value. the slope factors imply a linear correction, howe ver the implementation is set in steps of 30 mv (parameter n in table 27 on page 33 ). remark: after reset, v lcd is fixed because the vpr[7:0] bit field is reset logic 0. the value of vt[7:0] is generated by the rese t value of td[7:0] (40h, representing 20 ? c). temperature compensation is implemented by adding an offset vt[7:0] to the vpr[7:0] value. vt[7:0] is a two?s complement number that equals 0h at 20 ? c. the final result for v lcd calculation is an 8-bit positive number (see equation 6 on page 33 ). remark: care must be taken that the ranges of vpr[7:0] and vt[7:0] do not cause clipping and hence undesired resu lts. the device will not permit overflow or underflow and will clamp results to eith er end of the range. table 29. temperature coefficients sla[2:0] to sld[2:0] value corresponding slope factor (mv/ ? c) temperature coefficients ma, mb, mc, md [1] 000 [2] 00 . 0 0 001 ? 4 ? 0.125 010 ? 8 ? 0.25 011 ? 16 ? 0.5 100 ? 40 ? 1.25 101 +4 0.125 110 +8 0.25 111 +16 0.5 fig 30. example of segmented temperature coefficients mx 0.9375 0.03 ---------------- slope 1000 ------------- - ? = temperature ( c) ?40 50 ?10 013aaa261 td[7:0] 0h 60h 20h v lcd with temperature compensation (v) zero offset at 20 c 79 20 7fh 40h mc ma md mb sla slb slc sld
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 40 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the v offset(lcd) value can be calculated with the equations given in ta b l e 3 0 : (12) [1] no temperature compensation is possible above 80 ? c. above this value, the system maintains the compensation value from 80 ? c. example : assumed that t amb = ? 8 ? c; td[7:0] = 22h; mb = ? 0.5: (13) the vt[7:0] term is calculated using the digital temperature value td[7:0] which is provided by the temperature measurement block ( section 8.4.7 ). therefore the accuracy of the temperature measurement block (t acc , see table 35 on page 57 ) will be directly translated to the lcd voltage deviation ? v lcd . since vt[7:0] = f[t,slope] and t acc = ? 6 ? c then , where slope has one of the possible values specified in ta b l e 2 9 . this term will be added to the total lcd voltage deviation ? v offset(lcd)tot over the temperature range. so the total v lcd offset will be: . 8.5 oscillator the internal logic and lcd drive signals of the pca9620 are timed by a frequency f clk which either is the built -in oscillator frequency f osc or equals an external clock frequency. 8.5.1 internal oscillator when the internal oscillator is us ed, it is possible to make the clock signal available on pin clk by using the oscilla tor-ctrl command (see table 7 on page 8 ). if this is not intended, pin clk should be left open. at power-on the signal at pin clk is disabled and pin clk is in 3-state. the duty cycle of the output clock provided on the clk pin is not always 50 : 50. table 17 on page 11 shows the expected duty cycle for each of the chosen frame frequencies. 8.5.2 external clock in applications where an extern al clock needs to be applied to the pca9620, bit osc (see table 7 on page 8 ) must be set logic 1. in this case pin clk becomes an input. table 30. calculation of the temperature compensated voltage v t temperature range td[7:0] offset equa tion for v t t ? ? 40 ?c0 h ? 40 ?c ? t ?? 10 ? c 0h to 20h ? 10 ?c < t ? 20 ? c 21h to 40h 20 ? c < t ? 50 ?c 41h to 60h 50 ? c < t < 80 ?c 61h to 7eh 80 ?c ? t7 f h [1] v offset lcd ?? mv t ? = v t 32 ? ma ? 32 mb ? ? = v t td 7:0 ?? 32 ? ?? ma 32 mb ? ? ? = v t td 7:0 ?? 64 ? ?? ?? mb ? = v t td 7:0 ?? 64 ? ?? mc ? = v t td 7:0 ?? 96 ? ?? md ? 32 mc ? + = v t 31 md ? 32 + mc ? = v offset lcd ?? mv t ? mtd [7:0] 64 ? ?? mb ? ? 30mv 34 64 ? ?? 0.5 ? ? ?? ? 30mv 30 ? 0.5 ? ?? 450mv == = = = ? v t t acc slope ? = ? v offset lcd ?? tot ? v lcd ? v t +=
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 41 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the clk signal is a signal that is fed into the v dd1 domain so it must have an amplitude equal to the v dd1 voltage supplied to the chip and be referenced to v ss . the clock frequency (f clk ) determines the lcd frame frequency f fr . remark: if an external clock is used then this clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. removal of the clock is possibl e when following the correct procedures. see figure 13 on page 21 and figure 14 on page 22 . 8.5.3 timing and frame frequency the timing of the pca9620 organizes the internal data flow of the device. it includes the transfer of display data from the display ram to the display segment outputs. the timing also generates the lcd frame frequency which it derives as an integer division of the clock frequency. the frame frequency is a fixe d division of the internal clock or of the frequency applied to pin clk when an external clock is used: (14) when the internal clock is used, the clock and frame frequency can be programmed by software such that the nominal frame frequency can be chosen in steps of 10 hz in the range of 60 hz to 300 hz (see table 17 on page 11 ). furthermore the nominal frame frequency is factory-calibra ted with an accuracy of ? 15 %. when the internal clock is enabled at pin clk by using bit coe, the duty ratio of the clock may change when choosing different values for the frame frequency prescaler. table 17 on page 11 shows the different output duty ratios for each frame frequency prescaler setting. 8.6 backplane outputs the lcd drive section includes eight back plane outputs: bp0 to bp7. the backplane output signals are generated based on t he selected lcd mult iplex drive mode. ta b l e 3 1 describes which outputs are active for each of the multiplex drive modes and what signal is generated. [1] these pins may optionally be connected to the disp lay to improve drive strength. connect only with the corresponding output pin carrying the same signal. if not required, they can be left open-circuit. f fr f clk 48 ------- = table 31. mapping of output pins and corresponding output signals with respect to the multiplex driving mode multiplex drive mode output pin bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 signal 1:8 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 1:6 bp0 bp1 bp2 bp3 bp4 bp5 bp0 [1] bp1 [1] 1:4 bp0 bp1 bp2 bp3 bp0 [1] bp1 [1] bp2 [1] bp3 [1] 1:2 bp0 bp1 bp0 [1] bp1 [1] bp0 [1] bp1 [1] bp0 [1] bp1 [1] static bp0 bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1]
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 42 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.7 segment outputs the lcd drive section includes 60 segment ou tputs (s0 to s59) which must be connected directly to the lcd. the segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. when less than 60 segment outputs are required, the unused segment outputs must be left open-circuit. 8.8 display register the display register holds the display data while the corresponding multiplex signals are generated. 8.9 display ram the display ram is a static 60 ? 8-bit ram which stores lcd data. logic 1 in the ram bit map indicates the on-state of the corresponding lcd element; similarly, logic 0 indicates the off-state. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. the display ram bit map, figure 31 , shows row 0 to row 7 which correspond with the backplane outputs bp0 to bp7, and column 0 to column 59 which correspond with the segment outputs s0 to s59. in multiplexed lcd applications, the data of each row of the display ram is time-multiplexed with the corresponding backplane (row 0 with bp0, row 1 with bp1, and so on). when display data is transmitted to the pca9620, the display bytes received are stored in the display ram in accordance with the select ed lcd multiplex drive mode. the data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes.
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 43 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.9.1 data pointer the addressing mechanism for the display ram is realized using the data pointer. it allows the loading of an individual display data by te, or a series of display data bytes into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command. following this command, an arriving data byte is stored starting at the display ra m address indicated by the data pointer. the display ram bitmap shows the direct relationship between the display ram column and the segment outputs, between the bits in a ram row and the backplane outputs, and between the ram rows and banks. fig 31. display ram bitmap display ram columns/segment outputs (s) display ram rows/ backplane outputs (bp) 013aaa262 columns rows 0 1 2 3 4 5 6 7 012 34 55 56 57 58 59 0 1 2 3 4 5 6 7 012 34 55 56 57 58 59 0 1 2 3 4 5 6 7 012 34 55 56 57 58 59 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 0 bank 2 bank 4 bank 6 bank 0 bank 4 static drive mode multiplex 1:2 drive mode multiplex 1:4 drive mode
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 44 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the data pointer is automatically increm ented in accordance with the chosen lcd multiplex drive mode configuration. that is, af ter each byte is stored, the contents of the data pointer are incremented ? by eight (static drive mode) ? by four (1:2 multiplex drive mode) ? by two (1:4 multiplex drive mode) ? by one or two (1:6 multiplex drive mode), see figure 38 on page 47 ? by one (1:8 mult iplex drive mode) if the data pointer reaches the end of the ram row, it is automatically wrapped around to address 0. this means that it can be continuously written to or read from the display ram. the data pointer should always be set to an address where the remaining ram is divisible by eight because odd bi ts will be discarded (see figure 33 ). this behavior is only shown in static drive mode because the 60 ram cells cannot be divided by eight without remainder. if an i 2 c-bus data access is terminated early, then the state of the data pointer is unknown. the data pointer must then be re-written before further ram accesses. 8.9.1.1 ram filling in static drive mode in the static drive mode the eight transmitte d data bits are placed in eight successive display ram columns in row 0 (see figure 32 ). in order to fill the whole ram row, 8 bytes must be sent to the pca9620, but the last 4 bits from the last byte are discarded, and the data pointer is wrapped around to column 0 to start a possible ram content update (see figure 33 ). fig 32. display ram filling order in static drive mode 0 1 2 3 4 5 6 7 55 56 57 58 59 b0b1b2b3b4b5b6b7 0 msb lsb transmitted data byte display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa263 b0b1b2b3b4b5b6b7
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 45 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.9.1.2 ram filling in 1:2 multiplex drive mode in the 1:2 multiplex drive mode the eight tr ansmitted data bits are placed in four successive display ram columns of two rows (see figure 34 ). in order to fill the whole two ra m rows 15 bytes need to be se nt to the pca9620. after the last byte sent, the data pointer is wrapped around to column 0 to start a possible ram content update (see figure 35 ). even if a data byte is transmitted during the wrapping of the data pointer, then a ll the bits in the byte will be written correctly. 8.9.1.3 ram filling in 1:4 multiplex drive mode in the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display ram colu mns of four rows (see figure 36 ). fig 33. discarded bits and data pointer wrap around at the end of data transmission 01234567 4849505152 display ram data pointer 53 54 55 56 57 58 59 0 a7 a6 a5 a4 a3 a2 a1 a0 f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0 discarded wrap around 013aaa287 fig 34. display ram filling orde r in 1:2 multiplex drive mode fig 35. data pointer wrap around in 1:2 multiplex drive mode 012 34 56 7 5556575859 b0b1b2b3b4b5b6b7 0 1 b7 b6 b5 b4 b3 b2 b1 b0 lsb msb transmitted data byte 013aaa264 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 012 34 56 7 5556575859 0 1 b7 b6 b5 b4 b3 b2 b1 b0 display ram data pointer wrap around 013aaa288
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 46 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial in order to fill the whole four ram rows 30 bytes need to be sent to the pca9620. after the last byte sent, the data pointer is wrapped around to column 0 to start a possible ram content update (see figure 37 ). even if a data byte is transmitted during the wrapping of the data pointer, all the bits in the byte will be written correctly. 8.9.1.4 ram filling in 1:6 multiplex drive mode in the 1:6 multiplex drive mode the ram is organized in six rows and 60 columns. the eight transmitted data bits are placed in su ch a way, that a colu mn is filled up (see figure 38 ). fig 36. display ram filling orde r in 1:4 multiplex drive mode fig 37. data pointer wrap around in 1:4 multiplex drive mode 012 34 56 7 5556575859 b0b1b2b3b4b5b6b7 0 msb lsb 1 2 3 transmitted data byte b7 b6 b5 b4 b3 b2 b1 b0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa265 012 34 56 7 5556575859 0 1 2 3 b7 b6 b5 b4 b3 b2 b1 b0 display ram columns/segment outputs (s) columns display ram data pointer 013aaa289 wrap around
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 47 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the remaining bits are wrappe d up into the next column. in order to fill the whole ram addresses 45 bytes need to be sent to the pca9620. after the last byte sent, the data pointer is wrapped around to column 0 to start a possible ram content update (see figure 39 ). even if a data byte is transmitted du ring the wrapping of the data pointer, all the bits in the byte will be written correctly. 8.9.1.5 ram filling in 1:8 multiplex drive mode in the 1:8 multiplex drive mode the eight transmi tted data bits are placed into eight rows of one display ram column (see figure 40 ). fig 38. display ram filling orde r in 1:6 multiplex drive mode fig 39. data pointer wrap around in 1:6 multiplex drive mode 0 1 2 3 4 5 6 7 5556575859 a0a1a2a3a4a5a6a7 0 msb lsb 1 2 3 4 5 transmitted data bytes a7 a6 a5 a4 a3 a2 a1 a0 b0b1b2b3b4b5b6 c0c1c2c3c4c5c6 b7 c7 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa266 data pointer incrementation 0 1 2 3 4 5 6 7 5556575859 0 1 2 3 4 5 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 display ram data pointer 013aaa290 wrap around
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 48 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial in order to fill the whole ra m addresses 60 bytes need to be sent to the pca9620. after the last byte sent, the data pointer is wrapped around to column 0 to start a possible ram content update (see figure 41 ). in this case, there is no situation possible where a transmitted data byte can be written over the ram boundary. 8.9.2 bank selection a ram bank can be thought of as a collection of ram rows. the pca9620 includes a ram bank switching feature in the static , 1:2, and 1:4 multiplex drive modes. the ram bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. input and output banks can be set independently from one another with the input-bank-select and the output-bank-select commands; figure 42 shows the concept. fig 40. display ram filling orde r in 1:8 multiplex drive mode fig 41. data pointer wrap around in 1:8 multiplex drive mode 012 34 56 7 5556575859 b0b1b2b3b4b5b6b7 0 msb lsb 1 2 3 4 5 6 7 transmitted data byte b7 b6 b5 b4 b3 b2 b1 b0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa267 012 34 56 7 5556575859 0 1 2 3 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 display ram data pointer 013aaa291 a7 a6 a5 a4 a3 a2 a1 a0 wrap around
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 49 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial in figure 42 an example is shown for 1:4 multiplex drive mode. the displayed data is read from the first four rows of th e memory (bank 0), while the transmitted data is stored in the second four rows of the memory (bank 4) wh ich is currently not accessed for the reading. therefore different content can be loaded into the first and second four ram rows which will be immediately displayed on the lcd by switching it with th e output-bank-select command (see figure 43 ). 8.9.2.1 input-bank-select the input-bank-select command (see table 18 on page 12 ) loads display data into the display ram in accordan ce with the selected lcd drive configuration. ? in static drive mode, an individual content can be stored in each ram bank (bank 0 to bank 7 which corresponds to row 0 to row 7). ? in 1:2 multiplex drive mode, individual content for ram bank 0 (row 0 and row 1), ram bank 2 (row 2 and row 3), ram bank 4 (row 4 and 5) and ram bank 6 (row 6 and row 7) can be stored. ? in 1:4 multiplex drive mode individual conten t can be stored in ram bank 0 (row 0 to row 3) and ram bank 4 (row 4 to row 7). the input-bank-select command works in dependently to the output-bank-select. fig 42. example of bank sele ction in 1:4 multiplex mode fig 43. example of the input-bank-select an d the output-bank-se lect command with multiplex drive mode 1:4 microcontroller display ram bank 0 bank 4 013aaa422 input-bank-select command controls the input data path output-bank-select command controls the output data path 4 5 6 7 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa424 012 34 56 7 5556575859 0 1 2 3 to the lcd output ram bank input ram bank to the ram
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 50 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 8.9.2.2 output-bank-select the output-bank-select command (see table 19 on page 12 ) selects the display ram transferring it to the display register in accordance with the selected lcd drive configuration. ? in the static drive mode, it is possible to request the content of ram bank 1 (row 1) to ram bank 7 (row 7) for display instead of the default ram bank 0 (row 0). ? in 1:2 multiplex drive mode, the content of ram bank 2 (row 2 and row 3) or of ram bank 4 (row 4 and row 5) or of ram bank 6 (row 6 and row 7) may be selected instead of the default ram bank 0 (row 0 and row 1). ? in 1:4 multiplex drive mode, the content of ram bank 4 (row 4, 5, 6, and 7) may be selected instead of ram bank 0 (row 0, 1, 2, and 3). the output-bank-select command works independently to the input-bank-select.
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 51 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 9. i 2 c-bus interface characteristics the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each cloc k pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 44 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high is defined as the start condition (s). a low-to-high change of the data line while th e clock is high is defined as the stop condition (p). the start and stop conditions are shown in figure 45 . 9.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 46 . fig 44. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 45. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 52 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been clo cked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 47 . fig 46. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 47. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 53 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 9.5 i 2 c-bus controller the pca9620 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from pca9620 are the acknowledge signals and the temperature readout byte of the selected device. 9.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 9.7 i 2 c-bus slave address device selection depends on the i 2 c-bus slave address. four different i 2 c-bus slave addresses can be us ed to address the pca9620 (see ta b l e 3 2 ). the least significant bit of the slave address byte is bit r/w . bit 1 and bit 2 of the slave address are defined by connecting the inputs a0 and a1 to either v ss (logic 0) or v dd (logic 1). therefore, four instances of pca9620 can be distinguished on the same i 2 c-bus. 9.8 i 2 c-bus protocol table 32. i 2 c slave address slave address bit 7 6 5 4 3 2 1 0 msb lsb slave address 0 1 1 1 0 a1 a0 r/w fig 48. i 2 c-bus protocol write mode examples a) transmit two bytes of ram data 013aaa293 a 0 s01110 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s01110 0 01 a a a p ram data a b) transmit two command bytes command s01110 0 10 a a a p command a a c) transmit one command byte and two ram date bytes command s01110 0 10 00 01 a a a p ram data a ram data a a c o r s a 1 a 0 a 1 a 0 a 1 a 0 a 1
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 54 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial the i 2 c-bus protocol is shown in figure 48 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the four pca9620 slave addresses available. all pca9620?s with the corresponding a1 and a0 level acknowledge in parallel to the slave address, but all pc a9620 with the alternative a1 and a0 levels ignore the whole i 2 c-bus transfer. after acknowledgement, a contro l byte follows which defines if the next byte is ram or command information. the control byte also de fines if the next byte is a control byte or further ram or command data. in this way it is possible to configure the device and then fill the disp lay ram with little overhead. the display bytes are stored in the display ram at the address specified by the data pointer. the acknowledgement after each byte is made only by the (a0 and a1) addressed pca9620. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart an i 2 c-bus access. if a temperature readout (byte td[7:0]) is made the r/w bit must be logic 1 and then the next data byte following is provided by the pca9620 as shown in figure 50 . table 33. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - - not relevant fig 49. control byte format fig 50. i 2 c-bus protocol read mode mgl753 not relevant co 76 543210 rs msb lsb 013aaa294 a 0 s01110 1 slave address temperature readout byte m s b l s b a p r/w = 1 a 1 a acknowledge from pca9620 acknowledge from master
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 55 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 10. internal circuitry fig 51. device protection diagram a0, a1, t1, t2, clk v dd1 v ss 013aaa295 bp0 to bp7, s0 to s59 v lcd v ss t3, v lcd , sda, scl, v dd1 , v dd2 v ss
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 56 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 11. limiting values [1] pass level; human body model (hbm), according to ref. 7 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 8 ? jesd22-c101 ? . [3] pass level; latch-up testing according to ref. 9 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport requirements (see ref. 11 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. for long-term storage products divergent conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 34. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd1 supply voltage 1 analog and digital ? 0.5 +6.5 v v dd2 supply voltage 2 charge pump ? 0.5 +6.5 v i dd1 supply current 1 analog and digital ? 50 +50 ma i dd2 supply current 2 charge pump ? 50 +50 ma v lcd lcd supply voltage ? 0.5 +10 v i dd(lcd) lcd supply current ? 50 +50 ma v i input voltage on pins clk, sda, scl, a0, a1, t1, t2, t3 ? 0.5 +6.5 v i i input current ? 10 +10 ma v o output voltage on pins s0 to s59, bp0 to bp7 ? 0.5 +10 v on pins sda, clk ? 0.5 +6.5 v i o output current ? 10 +10 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p/out power dissipation per output -100mw v esd electrostatic discharge voltage hbm [1] - ? 4000 v cdm [2] - ? 1500 v i lu latch-up current [3] -100ma t stg storage temperature [4] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +105 ?c
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 57 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 12. static characteristics table 35. static characteristics v dd1 = 2.5 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd1 supply voltage 1 2.5 - 5.5 v v dd2 supply voltage 2 v dd2 ? v dd1 2.5 - 5.5 v v lcd lcd supply voltage v lcd ? v dd2 [1] 2.5 - 9.0 v ? v lcd lcd voltage variation v dd1 =v dd2 =5.0v; v lcd = 5.0 v to 9.0 v [2] t amb = ? 40 ? c to ? 10 ?c ? 130 - +130 mv t amb = ? 10 ? c to +70 ? c ? 70 - +70 mv t amb = +70 ? c to +105 ?c ? 100 - +100 mv v dd1 =v dd2 =3.0v; v lcd = 3.0 v to 8.5 v t amb = ? 40 ? c to +105 ?c ? 130 - +130 mv i dd(pd) power-down mode supply current on pin v dd1 [3] [4] -1.03.0 ? a i dd1 supply current 1 [4] [5] -100200 ? a i dd2 supply current 2 f osc = 9.6 khz charge pump off; external v lcd [4] [5] -0.53.0 ? a charge pump on; internal v lcd [4] [6] -250550 ? a i dd(lcd) lcd supply current external v lcd [4] [7] -125250 ? a i lcd(pd) power-down lcd current external v lcd [3] [4] -1235 ? a r o output resistance of charge pump (driving capabilities) charge pump set to 2 ? v dd2 ; i load = 3 ma (on pin v lcd ) [8] 0.2 0.85 1.6 k ? charge pump set to 3 ? v dd2 ; i load = 2 ma (on pin v lcd ) [9] 2.0 3.2 4.5 k ? t acc temperature accuracy read out temperature error; v dd1 =5.0v t amb = ? 40 ? c to +105 ?c ? 6-+6 ?c t amb =27 ?c ? 4-+4 ?c logic v i input voltage v ss ? 0.5 - v dd + 0.5 v v il low-level input voltage on pins clk, a1, a0 - - 0.3v dd v v ih high-level input voltage on pins clk, a1, a0 0.7v dd -- v v o output voltage ? 0.5 - v dd + 0.5 v v oh high-level output voltage on pin clk 0.8v dd -- v v ol low-level output voltage on pin clk - - 0.2v dd v i oh high-level output current output source current; v oh =4.6v; v dd = 5 v; on pin clk 1-- ma
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 58 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] when supplying external v lcd it must be v lcd ? v dd2 . also when using the internal charge pump to generate a certain v lcd , vpr[7:0] must be set to a value that the voltage is higher than v dd2 (see section 8.4.3 on page 33 ). [2] calibrated at testing stage with v dd1 = v dd2 = 5.0 v. v lcd temperature compensation is disabled. [3] display is disabled; i 2 c-bus inactive; temperat ure measurement disabled. [4] the typical value is defined at v dd1 =v dd2 = 5.0 v, v lcd = 7.0 v and 30 ? c. [5] temperature measurement enabled; 1:8 multiplex drive mode; 1 4 bias; display enabled; lcd outputs ar e open circuit; ram is all written with logic 1; inputs at v ss or v dd ; internal clock with the default prescale factor; i 2 c-bus inactive. [6] v dd2 = 5.0 v; charge pump set to 2 ? v dd2 ; vpr[7:0] set for v lcd = 7.0 v; 1:8 multiplex drive mode; 1 4 bias; temperature measurement enabled; display enabled; lcd outputs are open circuit; ram is all written with logic 1; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [7] external supplied v lcd = 7.0 v; 1:8 multiplex drive mode; 1 4 bias; temperature measurement enabled; display enabled; lcd outputs are open circuit; ram is all written with logic 1; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [8] v dd2 = 5.0 v; charge pump set to 2 ? v dd2 ; vpr[7:0] set for v lcd = 9.0 v; display disabled; cpf (see table 22 on page 13 ) set logic 0. [9] v dd2 = 4.0 v; charge pump set to 3 ? v dd2 ; vpr[7:0] set for v lcd = 9.0 v; display disabled; cpf (see table 22 on page 13 ) set logic 0. [10] if v dd1 > v por then no reset occurs. [11] in case of an esd event, the value may increase slightly. [12] variation between any 2 backplanes on a given voltage level; static measured. [13] variation between any 2 segments on a given voltage level; static measured. [14] outputs measured one at a time. i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pin clk 1-- ma v por power-on reset voltage [10] --1.6v i l leakage current v i =v dd or v ss ; on pins clk, a1, a0, t1, t2, t3 [11] -0- ? a i 2 c-bus; pins sda and scl v i input voltage v ss ? 0.5 - 5.5 v v il low-level input voltage pins scl, sda - - 0.3v dd v v ih high-level input voltage pins scl, sda 0.7v dd -- v v o output voltage pins scl, sda ? 0.5 - 5.5 v i ol low-level output current v ol = 0.4 v; v dd = 5 v; on pin sda 3 - - ma i l leakage current v i =v dd or v ss [11] -0- ? a lcd outputs ? v o output voltage variation on pins bp0 to bp7 [12] ? 15 - +15 mv on pins s0 to s59 [13] ? 15 - +15 mv r o output resistance v lcd = 7 v; on pins bp0 to bp7 [14] 0.3 0.8 1.5 k ? v lcd = 7 v; on pins s0 to s59 [14] 0.6 1.5 3 k ? table 35. static characteristics ?continued v dd1 = 2.5 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 59 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial (1) vpr[7:0] = 85h. (2) vpr[7:0] = 64h. (3) vpr[7:0] = a4h. temperature compensation disabled. fig 52. typical v lcd with respect to temperature v dd1 =5.0v. fig 53. typical i dd1 with respect to temperature temperature ( c) ?50 150 100 50 0 001aan026 6.8 7.3 6.3 7.8 8.3 v lcd (v) 5.8 (3) (1) (2) 001aan023 temperature ( c) ?40 120 80 40 0 80 100 120 i dd1 (a) 60
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 60 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial charge pump set to 2 ? v dd2 ; v lcd = 7.0 v; v dd1 =v dd2 =5.0v. fig 54. typical i dd2 with respect to temperature v lcd = 7.0 v, external supplied; v dd1 =v dd2 = 5.0 v; display enabled, but no display attached. fig 55. typical i lcd with respect to temperature temperature ( c) ?40 120 80 40 0 001aan024 180 220 140 260 300 i dd2 (a) 100 001aan025 temperature ( c) ?40 120 80 40 0 100 120 140 i lcd (a) 80
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 61 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 13. dynamic characteristics [1] internal calibration made with otp so that the maximum variation is ? 15 % over whole temperature and voltage range. the typical f osc generates a typical frame frequency of 200 hz when t he default frequency division factor is used (see section 8.5.3 on page 41 ). [2] the typical value is defined at v dd1 =v dd2 = 5.0 v and 30 ? c. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . [4] t vd;dat = minimum time for valid sda output following scl low. [5] t vd;ack = time for acknowledgement signal from scl low to sda output low. table 36. dynamic characteristics v dd1 = 2.5 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit f osc oscillator frequency on pin clk; see table 17 on page 11 [1] [2] 8160 9600 11040 hz f clk(ext) external clock frequency 450 - 14500 hz t clk(h) high-level clock time external clock source used 33 - - ? s t clk(l) low-level clock time 33 - - ? s timing characteristics: i 2 c-bus [3] f scl scl frequency - - 400 khz t buf bus free time between a stop and start condition 1.3 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t vd;dat data valid time [4] --0.9 ? s t vd;ack data valid acknowledge time [5] --0.9 ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t f fall time of both sda and scl signals - - 0.3 ? s t r rise time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line --400pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t w(spike) spike pulse width - - 50 ns
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 62 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 14. test information 14.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. fig 56. driver timing waveforms fig 57. i 2 c-bus timing waveforms 013aaa296 clk t clk(h) t clk(l) 1/f clk 0.7 v dd 0.3 v dd scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 013aaa417 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 63 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 15. package outline fig 58. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1)(1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 64 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 16. bare die outline fig 59. bare die outline of pca9620 references outline version european projection issue date iec jedec jeita pca9620u pca9620u_do bare die; 80 bonding pads pca9620u detail x e x 0 0 y x d e (1) a p 2 p 1 p 4 p 3 1 20 21 40 41 60 61 80 notes 1. marking code: pc9620-1 11-09-15 11-09-26 pin 1 index
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 65 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] dimension includes saw lane (70 ? m). [2] see table 38 . [3] p 1 and p 3 : pad size. [4] p 2 and p 4 : passivation opening. table 37. dimensions of pca9620 original dimensions are in mm. unit (mm) a d [1] e [1] e [2] p 1 [3] p 2 [4] p 3 [3] p 4 [4] max---0.203---- nom 0.38 3.166 3.166 - 0.065 0.056 0.065 0.056 min---0.075---- table 38. bonding pad description of pca9620 all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 59 . symbol pad location pitch description x( ? m) y( ? m) x( ? m) y( ? m) s20 1 ? 1497.3 1208.7 - - lcd segment output s21 2 ? 1497.3 1086.3 0 122.4 s22 3 ? 1497.3 963.9 0 122.4 s23 4 ? 1497.3 841.5 0 122.4 s24 5 ? 1497.3 719.1 0 122.4 s25 6 ? 1497.3 568.8 0 150.3 s26 7 ? 1497.3 446.4 0 122.4 s27 8 ? 1497.3 324.0 0 122.4 s28 9 ? 1497.3 201.6 0 122.4 s29 10 ? 1497.3 79.2 0 150.3 s30 11 ? 1497.3 ? 71.1 0 122.4 s31 12 ? 1497.3 ? 193.5 0 122.4 s32 13 ? 1497.3 ? 315.9 0 122.4 s33 14 ? 1497.3 ? 438.3 0 122.4 s34 15 ? 1497.3 ? 560.7 0 122.4 s35 16 ? 1497.3 ? 711.0 0 122.4 s36 17 ? 1497.3 ? 833.4 0 122.4 s37 18 ? 1497.3 ? 955.8 0 122.4 s38 19 ? 1497.3 ? 1078.2 0 122.4 s39 20 ? 1497.3 ? 1200.6 0 122.4 s40 21 ? 1204.2 ? 1497.3 - - s41 22 ? 1081.8 ? 1497.3 122.4 0 s42 23 ? 959.4 ? 1497.3 122.4 0 s43 24 ? 837.0 ? 1 497.3 122.4 0 s44 25 ? 714.6 ? 1497.3 122.4 0 s45 26 ? 564.3 ? 1497.3 150.3 0 s46 27 ? 441.9 ? 1497.3 122.4 0
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 66 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial s47 28 ? 319.5 ? 1497.3 122.4 0 lcd segment output s48 29 ? 197.1 ? 1497.3 122.4 0 s49 30 ? 74.7 ? 1497.3 122.4 0 s50 31 75.6 ? 1497.3 150.3 0 s51 32 198.0 ? 1497.3 122.4 0 s52 33 320.4 ? 1497.3 122.4 0 s53 34 442.8 ? 1497.3 122.4 0 s54 35 565.2 ? 1497.3 122.4 0 s55 36 715.5 ? 1497.3 150.3 0 s56 37 837.9 ? 1497.3 122.4 0 s57 38 960.3 ? 1497.3 122.4 0 s58 39 1082.7 ? 1497.3 122.4 0 s59 40 1205.1 ? 1497.3 122.4 0 bp0 41 1497.3 ? 1201.5 - - lcd backplane output bp1 42 1497.3 ? 1077.3 0 124.2 bp2 43 1497.3 ? 953.1 0 124.2 bp3 44 1497.3 ? 828.9 0 124.2 bp4 45 1497.3 ? 676.8 0 152.1 bp5 46 1497.3 ? 552.6 0 124.2 bp6 47 1497.3 ? 428.4 0 124.2 bp7 48 1497.3 ? 304.2 0 124.2 v lcd 49 1497.3 ? 171.9 0 132.3 lcd supply voltage v dd2 50 1497.3 ? 47.7 0 124.2 supply voltage 2 (charge pump) v dd1 51 1497.3 76.5 0 124.2 supply voltage 1 (analog and digital) v ss 52 1497.3 166.5 0 90 ground supply voltage t1 53 1497.3 241.2 0 74.7 test pin t2 54 1497.3 315.9 0 74.7 t3 55 1497.3 430.2 0 114.3 clk 56 1497.3 620.1 0 189.9 internal oscillator output, external oscillator input a0 57 1497.3 729.9 0 109.8 i 2 c-bus slave address selection bit a1 58 1497.3 806.4 0 76.5 scl 59 1497.3 913.5 0 107.1 i 2 c-bus serial clock sda 60 1497.3 1116.9 0 203.4 i 2 c-bus serial data s0 61 1205.1 1497.3 - - lcd segment output s1 62 1082.7 1497.3 122.4 0 s2 63 960.3 1497.3 122.4 0 s3 64 837.9 1497.3 122.4 0 s4 65 715.5 1497.3 122.4 0 table 38. bonding pad description of pca9620 ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 59 . symbol pad location pitch description x( ? m) y( ? m) x( ? m) y( ? m)
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 67 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial [1] the x/y coordinates of the alignment mark loca tion represent the position of the ref point (see figure 60 ) with respect to the center (x/y = 0) of the chip; see figure 59 . [2] the x/y values of the dimensions represent the ext ensions of the alignment mark in direction of the coordinate axis (see figure 60 ). s5 66 565.2 1497.3 150.3 0 lcd segment output s6 67 442.8 1497.3 122.4 0 s7 68 320.4 1497.3 122.4 0 s8 69 198.0 1497.3 122.4 0 s9 70 75.6 1497.3 122.4 0 s10 71 ? 74.7 1497.3 150.3 0 s11 72 ? 197.1 1497.3 122.4 0 s12 73 ? 319.5 1497.3 122.4 0 s13 74 ? 441.9 1497.3 122.4 0 s14 75 ? 564.3 1497.3 122.4 0 s15 76 ? 714.6 1497.3 150.3 0 s16 77 ? 837.0 1497.3 122.4 0 s17 78 ? 959.4 1497.3 122.4 0 s18 79 ? 1081.8 1497.3 122.4 0 s19 80 ? 1204.2 1497.3 122.4 0 table 38. bonding pad description of pca9620 ?continued all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 59 . symbol pad location pitch description x( ? m) y( ? m) x( ? m) y( ? m) table 39. alignment mark dimension and location of all pca9620 types coordinates x (? m) y (? m) location [1] 1495.8 1395.0 dimension [2] 52.5 63.72 fig 60. alignment mark 013aaa511 ref y x
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 68 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 17. packing information 17.1 wafer information wafer thickness, see table 40 . fig 61. wafer layout of pca9620 x saw lane detail x marking code straight edge of the wafer 013aaa512 pin 1 18 m 70 m seal ring plus gap to active circuit ~18 mm 18 m 70 m
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 69 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: table 40. pca9620 wafer information type number wafer thickness wafer diameter marking of bad die pca9620/5ga/q1 0.687 mm 6 inch wafer mapping
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 70 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 62 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 1 and 42 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 62 . table 41. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 42. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 71 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 62. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 72 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 19. abbreviations table 43. abbreviations acronym description aec automotive electronics council cdm charged-device model dc direct current eprom erasable programmable read-only memory esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit lcd liquid crystal display lsb least significant bit msb most significant bit msl moisture sensitivity level mux multiplexer otp one time programmable pcb printed-circuit board por power-on reset rc resistance-capacitance ram random access memory rms root mean square scl serial clock line sda serial data line smd surface mount device
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 73 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 20. references [1] an10365 ? surface mount reflow soldering description [2] an10706 ? handling bare die [3] an10853 ? esd and emc sensitivity of ic [4] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [5] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [6] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [7] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [8] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [9] jesd78 ? ic latch-up test [10] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [11] nx3-00092 ? nxp store and transport requirements [12] snv-fa-01-02 ? marking formats integrated circuits [13] um10204 ? i 2 c-bus specification and user manual
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 74 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 21. revision history table 44. revision history document id release date data sheet status change notice supersedes pca9620 v.2 20111108 product data sheet - pca9620 v.1 modifications: ? adjusted specification of lcd voltage variation ? added bare die type and related information ? corrected equations of drive mode waveforms ? adjusted automotive qualification statement ? added comment to block diagram pca9620 v.1 20101209 product data sheet - -
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 75 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 22.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 22.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 76 of 78 nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. unless otherwise agreed in wr iting, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in su ch equipment or applications and therefore such inclusion and/or use is at the customer's own risk. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are da ta sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 22.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 23. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pca9620 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 november 2011 77 of 78 continued >> nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 7 8.1 commands of pca9620 . . . . . . . . . . . . . . . . . . 7 8.1.1 command: initialize . . . . . . . . . . . . . . . . . . . . . 7 8.1.2 command: otp-refresh . . . . . . . . . . . . . . . . . . 8 8.1.3 command: oscillator-ctrl . . . . . . . . . . . . . . . . . . 8 8.1.4 command: charge-pump-ctrl . . . . . . . . . . . . . . 9 8.1.5 command: temp-msr-ctrl . . . . . . . . . . . . . . . . . 9 8.1.6 command: set-vpr-msb and set-vpr-lsb . . 9 8.1.7 command: display-enable . . . . . . . . . . . . . . . 10 8.1.8 command: set-mux-mode . . . . . . . . . . . . . . . 10 8.1.9 command: set-bias-mode . . . . . . . . . . . . . . . 10 8.1.10 command: load-data-pointer . . . . . . . . . . . . . 10 8.1.11 command: frame-frequency . . . . . . . . . . . . . . 11 8.1.12 bank select commands . . . . . . . . . . . . . . . . . 12 8.1.12.1 command: input-bank-select . . . . . . . . . . . . . 12 8.1.12.2 command: output-bank-select . . . . . . . . . . . . 12 8.1.13 command: write-ram-data . . . . . . . . . . . . . . 13 8.1.14 command: temp-read. . . . . . . . . . . . . . . . . . . 13 8.1.15 command: invmode_cpf_ctrl . . . . . . . . . . . . 13 8.1.16 command: temp-filter . . . . . . . . . . . . . . . . . . . 14 8.2 possible display configurations . . . . . . . . . . . 14 8.3 start-up and shut-down. . . . . . . . . . . . . . . . . . 16 8.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . 16 8.3.2 recommended start-up sequences . . . . . . . . 18 8.3.3 recommended power-down sequences . . . . 20 8.4 lcd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4.1 lcd voltage selector . . . . . . . . . . . . . . . . . . . 22 8.4.1.1 electro-optical performance . . . . . . . . . . . . . . 24 8.4.2 lcd drive mode waveforms . . . . . . . . . . . . . . 25 8.4.2.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 25 8.4.2.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 26 8.4.2.3 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 28 8.4.2.4 1:6 multiplex drive mode. . . . . . . . . . . . . . . . . 29 8.4.2.5 1:8 multiplex drive mode. . . . . . . . . . . . . . . . . 31 8.4.3 v lcd generation . . . . . . . . . . . . . . . . . . . . . . . 33 8.4.4 external v lcd supply . . . . . . . . . . . . . . . . . . . 34 8.4.5 charge pump driving capability . . . . . . . . . . . 35 8.4.6 charge pump frequency settings and power efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.7 temperature readout . . . . . . . . . . . . . . . . . . . 37 8.4.8 temperature compensation of v lcd . . . . . . . . 38 8.5 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . 40 8.5.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5.3 timing and frame frequency . . . . . . . . . . . . . 41 8.6 backplane outputs . . . . . . . . . . . . . . . . . . . . . 41 8.7 segment outputs . . . . . . . . . . . . . . . . . . . . . . 42 8.8 display register . . . . . . . . . . . . . . . . . . . . . . . 42 8.9 display ram . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.9.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.9.1.1 ram filling in static drive mode . . . . . . . . . . . 44 8.9.1.2 ram filling in 1:2 multiplex drive mode . . . . . 45 8.9.1.3 ram filling in 1:4 multiplex drive mode . . . . . 45 8.9.1.4 ram filling in 1:6 multiplex drive mode . . . . . 46 8.9.1.5 ram filling in 1:8 multiplex drive mode . . . . . 47 8.9.2 bank selection . . . . . . . . . . . . . . . . . . . . . . . . 48 8.9.2.1 input-bank-select . . . . . . . . . . . . . . . . . . . . . . 49 8.9.2.2 output-bank-select. . . . . . . . . . . . . . . . . . . . . 50 9 i 2 c-bus interface characteristics . . . . . . . . . . 51 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 start and stop conditions. . . . . . . . . . . . . 51 9.3 system configuration . . . . . . . . . . . . . . . . . . . 51 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 53 9.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.7 i 2 c-bus slave address . . . . . . . . . . . . . . . . . . 53 9.8 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 53 10 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 55 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 56 12 static characteristics . . . . . . . . . . . . . . . . . . . 57 13 dynamic characteristics. . . . . . . . . . . . . . . . . 61 14 test information . . . . . . . . . . . . . . . . . . . . . . . 62 14.1 quality information . . . . . . . . . . . . . . . . . . . . . 62 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 63 16 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 64 17 packing information . . . . . . . . . . . . . . . . . . . . 68 17.1 wafer information. . . . . . . . . . . . . . . . . . . . . . 68 18 soldering of smd packages . . . . . . . . . . . . . . 69 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 69 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 69 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 69 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 70 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 72
nxp semiconductors pca9620 60 x 8 lcd high-drive segment driver for automotive and industrial ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 november 2011 document identifier: pca9620 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . 74 22 legal information. . . . . . . . . . . . . . . . . . . . . . . 75 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 75 22.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 22.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 76 23 contact information. . . . . . . . . . . . . . . . . . . . . 76 24 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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